The invention relates to a method of creating flat, crack-free low-dislocation-density mismatched semiconductor layers, and of controlling threading dislocation densities in Ge on Si using graded SiGe layers.
The progression of electronic and optoelectronic components and systems is creating a need for more complex system-level functions to be incorporated at the chip level. One of the effects of this demand is to bring ever-increasing pressure to use materials that are not lattice-matched to common substrates.
The technological significance of a totally miscible GeSi system has been well documented. In particular, relaxed graded GeSi buffers have been used as “substrates” for the growth of high electron mobility structures and for the integration of III-V devices on Si. The relaxed graded buffer introduces a 4% lattice mismatch between Si and Ge gradually, resulting in a disperse, three-dimensional misfit dislocation network. Strain-relieving glide of threading dislocations is facilitated, preventing the accumulation of mismatch strain. Because threading dislocations present in the initial layers can also be used to relieve strain in subsequent layers, the nucleation of additional dislocations is suppressed as the graded layer growth progresses. However, a complication arises during thick grades to high Ge concentrations.
The characteristic crosshatch surface roughness and the underlying strain fields of the misfit array can overlap, blocking threading dislocation glide and leading to dislocation pile-ups. The formation of these pile-ups necessitates the nucleation of additional threading dislocations, as the trapped threading dislocations can no longer contribute to strain relief. Growth on off-cut Si substrates has been shown to improve surface morphology and decrease the number of pileups, but not eliminate them entirely. Therefore, an increase in threading dislocation density and the number of pile-ups is always observed as the thickness of graded layers increases.